Simulating collective neutrinos oscillations on the Intel Many Integrated Core (MIC) architecture

TL;DR

This paper evaluates the performance of a specialized code for simulating neutrino oscillations on Intel's MIC architecture, demonstrating significant improvements over previous generations and highlighting optimization strategies for high-performance computing.

Contribution

Developed and optimized a new numerical code, XFLAT, for simulating neutrino oscillations on Intel MIC architecture, achieving substantial performance gains.

Findings

Performance improved by many folds compared to previous Xeon Phi generations

Optimized code using Structure of Array (SoA) for SIMD utilization

Benchmarked on NERSC Cori supercomputer with dual 68-core Xeon Phis

Abstract

We evaluate the second-generation Intel Xeon Phi coprocessor based on the Intel Many Integrated Core (MIC) architecture, aka the Knights Landing or KNL, for simulating neutrino oscillations in (core-collapse) supernovae. For this purpose we have developed a numerical code XFLAT which is optimized for the MIC architecture and which can run on both the homogeneous HPC platform with CPUs or Xeon Phis only and the hybrid platform with both CPUs and Xeon Phis. To efficiently utilize the SIMD (vector) units of the MIC architecture we implemented a design of Structure of Array (SoA) in the low-level module of the code. We benchmarked the code on the NERSC Cori supercomputer which is equipped with dual 68-core 7250 Xeon Phis. We find that compare to the first generation of the Xeon Phi (Knights Corner a.k.a KNC) the performance improves by many folds. Some of the problems that we encountered in this work may be solved with the advent of the new supernova model for neutrino oscillations and the next-generation Xeon Phi.