Erase-hidden and Drivability-improved Magnetic Non-Volatile Flip-Flops with NAND-SPIN Devices

TL;DR

This paper introduces a novel magnetic non-volatile flip-flop using NAND-SPIN devices, enhancing erase-hidden features and drivability, leading to improvements in power, delay, and area over traditional designs.

Contribution

It proposes a new magnetic NVFF based on NAND-SPIN technology with a unique erase operation, offering increased design flexibility and performance benefits.

Findings

Achieves lower power consumption compared to conventional designs.

Reduces delay and area through innovative device architecture.

Improves drivability and erase-hidden features in NVFFs.

Abstract

Non-volatile flip-flops (NVFFs) using power gating techniques promise to overcome the soaring leakage power consumption issue with the scaling of CMOS technology. Magnetic tunnel junction (MTJ) is a good candidate for constructing the NVFF thanks to its low power, high speed, good CMOS compatibility, etc. In this paper, we propose a novel magnetic NVFF based on an emerging memory device called NAND-SPIN. The data writing of NAND-SPIN is achieved by successively applying two unidirectional currents, which respectively generate the spin orbit torque (SOT) and spin transfer torque (STT) for erase and programming operations. This characteristic allows us to design an erase-hidden and drivability-improved magnetic NVFF. Furthermore, more design flexibility could be obtained since the backup operation of the proposed NVFF is not limited by the inherent slave latch. Simulation results show that our proposed NVFF achieves performance improvement in terms of power, delay and area, compared with conventional slave-latch-driven SOT-NVFF designs.