A sparse spin qubit array with integrated control electronics

TL;DR

This paper proposes a sparse spin-qubit architecture with integrated control electronics to reduce wiring complexity, advancing the development of scalable CMOS quantum computers.

Contribution

It introduces a novel sparse architecture that integrates control electronics, significantly decreasing off-chip wiring and addressing scalability challenges in quantum computing.

Findings

Reduces off-chip wiring by integrating control electronics

Demonstrates feasibility of CMOS-compatible quantum hardware

Addresses scalability issues in quantum computer design

Abstract

Current implementations of quantum computers suffer from large numbers of control lines per qubit, becoming unmanageable with system scale up. Here, we discuss a sparse spin-qubit architecture featuring integrated control electronics significantly reducing the off-chip wire count. This quantum-classical hardware integration closes the feasibility gap towards a CMOS quantum computer.