CAD Tool Design Space Exploration via Bayesian Optimization

TL;DR

This paper presents an automatic design space exploration method using Bayesian optimization to efficiently tune EDA tool parameters, reducing manual effort and improving circuit synthesis quality in advanced technology nodes.

Contribution

It introduces a Bayesian optimization framework with Gaussian process regression for EDA parameter tuning, demonstrated on a 64-bit prefix adder design.

Findings

Bayesian optimization effectively explores the design space.

Significant reduction in manual tuning efforts.

Potential to accelerate advanced technology node design flows.

Abstract

The design complexity is increasing as the technology node keeps scaling down. As a result, the electronic design automation (EDA) tools also become more and more complex. There are lots of parameters involved in EDA tools, which results in a huge design space. What's worse, the runtime cost of the EDA flow also goes up as the complexity increases, thus exhaustive exploration is prohibitive for modern designs. Therefore, an efficient design space exploration methodology is of great importance in advanced designs. In this paper we target at an automatic flow for reducing manual tuning efforts to achieve high quality circuits synthesis outcomes. It is based on Bayesian optimization which is a promising technique for optimizing black-box functions that are expensive to evaluate. Gaussian process regression is leveraged as the surrogate model in Bayesian optimization framework. In this work, we use 64-bit prefix adder design as a case study. We demonstrate that the Bayesian optimization is efficient and effective for performing design space exploration on EDA tool parameters, which has great potential for accelerating the design flow in advanced technology nodes.