Integration and Evaluation of Quantum Accelerators for Data-Driven User Functions

TL;DR

This paper proposes a system architecture for integrating quantum accelerators into industry-grade systems and evaluates their performance using real-world data, demonstrating feasibility and comparable accuracy to classical methods.

Contribution

It introduces a novel system architecture for quantum accelerator integration and evaluates quantum-enhanced kernels on real-world data within this framework.

Findings

Quantum-enhanced kernel performs at least as well as classical kernels.

Low reduction in accuracy and latency on IBM quantum accelerator.

Feasibility of integrating NISQ devices into industry systems.

Abstract

Quantum computers hold great promise for accelerating computationally challenging algorithms on noisy intermediate-scale quantum (NISQ) devices in the upcoming years. Much attention of the current research is directed to algorithmic research on artificial data that is disconnected from live systems, such as optimization of systems or training of learning algorithms. In this paper we investigate the integration of quantum systems into industry-grade system architectures. In this work we propose a system architecture for the integration of quantum accelerators. In order to evaluate our proposed system architecture we implemented various algorithms including a classical system, a gate-based quantum accelerator and a quantum annealer. This algorithm automates user habits using data-driven functions trained on real-world data. This also includes an evaluation of the quantum enhanced kernel, that previously was only evaluated on artificial data. In our evaluation, we showed that the quantum-enhanced kernel performs at least equally well to a classical state-of-the-art kernel. We also showed a low reduction in accuracy and latency numbers within acceptable bounds when running on the gate-based IBM quantum accelerator. We, therefore, conclude it is feasible to integrate NISQ-era devices in industry-grade system architecture in preparation for future hardware improvements.