Implementation of the XY interaction family with calibration of a single pulse

TL;DR

This paper demonstrates the implementation of a family of XY entangling gates in superconducting qubits, using a single calibration pulse, leading to high fidelity and reduced circuit depth for quantum algorithms.

Contribution

The authors introduce a method to implement the full XY gate family with a single pulse calibration, enhancing expressiveness and efficiency in quantum circuits.

Findings

Achieved high gate fidelities approaching coherence limits.

Demonstrated circuit depth reduction in quantum optimization algorithms.

Implemented a calibration scheme requiring only a single pulse.

Abstract

Near-term applications of quantum information processors will rely on optimized circuit implementations to minimize gate depth and therefore mitigate the impact of gate errors in noisy intermediate-scale quantum (NISQ) computers. More expressive gate sets can significantly reduce the gate depth of generic circuits. Similarly, structured algorithms can benefit from a gate set that more directly matches the symmetries of the problem. The XY interaction generates a family of gates that provides expressiveness well tailored to quantum chemistry as well as to combinatorial optimization problems, while also offering reductions in circuit depth for more generic circuits. Here we implement the full family of XY entangling gates in a transmon-based superconducting qubit architecture. We use a composite pulse scheme that requires calibration of only a single gate pulse and maintains constant gate time for all members of the family. This allows us to maintain a high fidelity implementation of the gate across all entangling angles. The average fidelity of gates sampled from this family ranges from $95.67 \pm 0.60\%$ to $99.01 \pm 0.15\%$, with a median fidelity of $97.35 \pm 0.17\%$, which approaches the coherence-limited gate fidelity of the qubit pair. We furthermore demonstrate the utility of XY in a quantum approximation optimization algorithm in enabling circuit depth reductions as compared to the CZ only case.