Write and Read Channel Models for 1S1R Crossbar Resistive Memory with High Line Resistance

TL;DR

This paper develops statistical channel models for 1S1R crossbar resistive memory considering line resistance and variability, enabling better understanding of reliability issues and guiding design improvements.

Contribution

It introduces BAC-based models that quantify write/read margins affected by line resistance and variability, aiding in reliability assessment and coding strategy design.

Findings

Bit-error rates are highly non-uniform across the array.

Models enable evaluation of reliability trade-offs with design parameters.

Quantitative tools for optimizing crossbar memory reliability.

Abstract

Crossbar resistive memory with 1 Selector 1 Resistor (1S1R) structure is attractive for low-cost and high-density nonvolatile memory applications. As technology scales down to the single-nm regime, the increasing resistivity of wordline/bitline becomes a limiting factor to device reliability. This paper presents write/read communication channels while considering the line resistance and device variabilities by statistically relating the degraded write/read margins and the channel parameters. Binary asymmetric channel (BAC) models are proposed for the write/read operations. Simulations based on these models suggest that the bit-error rate of devices are highly non-uniform across the memory array. These models provide quantitative tools for evaluating the trade-offs between memory reliability and design parameters, such as array size, technology nodes, and aspect ratio, and also for designing coding-theoretic solutions that would be most effective for crossbar memory.