A Novel FPGA-Based High Throughput Accelerator For Binary Search Trees

TL;DR

This paper introduces a highly parallel FPGA-based accelerator for binary search trees that leverages novel tree partitioning and duplication techniques to significantly boost search throughput.

Contribution

It proposes new FPGA-based methods including tree duplication and hybrid partitioning to enhance BST search performance, achieving up to 8X throughput improvement.

Findings

Up to 8X throughput gain over baseline implementation.

Effective techniques to reduce stalling during parallel searches.

Utilization of FPGA on-chip memory architecture for acceleration.

Abstract

This paper presents a deeply pipelined and massively parallel Binary Search Tree (BST) accelerator for Field Programmable Gate Arrays (FPGAs). Our design relies on the extremely parallel on-chip memory, or Block RAMs (BRAMs) architecture of FPGAs. To achieve significant throughput for the search operation on BST, we present several novel mechanisms including tree duplication as well as horizontal, duplicated, and hybrid (horizontal-vertical) tree partitioning. Also, we present efficient techniques to decrease the stalling rates that can occur during the parallel tree search. By combining these techniques and implementations on Xilinx Virtex-7 VC709 platform, we achieve up to 8X throughput improvement gain in comparison to the baseline implementation, i.e., a fully-pipelined FPGA-based accelerator.