A 130-MS/s 10-Bit Asynchronous SAR ADC with 55.2 dB SNDR

TL;DR

This paper introduces a low-power, high-speed 10-bit asynchronous SAR ADC fabricated in 90 nm CMOS, achieving 130 MS/s, 55.2 dB SNDR, and an FOM of 50.9 fJ/MHz, suitable for high-speed applications.

Contribution

The paper presents a novel asynchronous SAR ADC design with optimized power and speed performance in 90 nm CMOS technology.

Findings

Achieves 130 MS/s sampling rate at 10 bits resolution.

Consumes only 860 μW power at 130 MS/s.

Attains an SNDR of 55.2 dB and an FOM of 50.9 fJ/MHz.

Abstract

This paper presents a low-power 10-bit 130-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 90 nm CMOS process. The proposed asynchronous ADC consists of a comparator, SAR logic block and two control blocks for the capacitive digital to analog converters (DAC). At a 1.2 V supply and 130 MS/s, the ADC achieves an SNDR of 55.2 dB and consumes 860 uW, resulting in a figure of merit (FOM) of 50.9 fJ/MHz. It achieves an ENOB of 8.8 bits with a differential input range of 1570 mV.