A binary-activation, multi-level weight RNN and training algorithm for ADC-/DAC-free and noise-resilient processing-in-memory inference with eNVM

TL;DR

This paper introduces a training algorithm for neural networks with binary activations and multi-level weights, enabling efficient, noise-resilient processing-in-memory inference using embedded nonvolatile memories, suitable for RNNs and other architectures.

Contribution

The proposed algorithm supports binary activations and multi-level weights, improving accuracy and noise robustness for PIM neural network hardware, including recurrent networks.

Findings

Achieves high inference accuracy on RNN-based trigger-word detection

Demonstrates robustness against hardware non-idealities

Enables ADC-/DAC-free processing-in-memory circuits

Abstract

We propose a new algorithm for training neural networks with binary activations and multi-level weights, which enables efficient processing-in-memory circuits with embedded nonvolatile memories (eNVM). Binary activations obviate costly DACs and ADCs. Multi-level weights leverage multi-level eNVM cells. Compared to existing algorithms, our method not only works for feed-forward networks (e.g., fully-connected and convolutional), but also achieves higher accuracy and noise resilience for recurrent networks. In particular, we present an RNN-based trigger-word detection PIM accelerator, with detailed hardware noise models and circuit co-design techniques, and validate our algorithm's high inference accuracy and robustness against a variety of real hardware non-idealities.