Multi-Domain Negative Capacitance Effects in Metal-Ferroelectric-Insulator-Semiconductor (Metal) Stacks: A Phase-field Simulation Based Study

TL;DR

This study uses phase-field simulations to analyze negative capacitance effects in multi-domain ferroelectric stacks, revealing how domain walls influence charge response and potential profiles in metal-insulator-semiconductor devices.

Contribution

It introduces a detailed phase-field simulation approach to understand multi-domain ferroelectric negative capacitance effects in MFIM and MFIS stacks, highlighting the role of domain walls and material parameters.

Findings

Multi-domain ferroelectric states induce negative permittivity locally.

Enhanced charge response observed in MFIM and MFIS stacks due to domain-wall effects.

Potential profiles in semiconductors are non-homogeneous, affecting carrier distribution.

Abstract

In this work, we analyze the ferroelectric (FE) domain-wall (DW) induced negative capacitance (NC) effect in Metal-FE-Insulator-Metal (MFIM) and Metal-FE-Insulator-Semiconductor (MFIS) stacks. Our analysis is based on 2D phase field simulations. Considering HZO as the FE material, we study 180 FE domain formation in MFIM and MFIS stacks and their voltage-dependent DW motion. Our analysis signifies that, when FE is in multi-domain (MD) state with soft-DW, the stored energy in the DW leads to non-hysteretic NC effect in FE, which provides an enhanced charge response in the MFIM stack, compared to Metal-Insulator-Metal. According to our analysis, the DW-induced NC effect yields local negative permittivity in FE in the domain and DW regions, which leads to an average negative effective permittivity in FE. Furthermore, we show that the NC trajectory of FE is dependent on its thickness, the gradient energy coefficient and the in-plane permittivity of the underline DE material but not on the DE thickness. Similar to MFIM, MFIS also exhibits an enhancement in the overall charge response and the capacitance compared to MOS capacitor. At the same time, the MD state of FE induces non-homogenous potential profile across the underlying DE and semiconductor layer. In the low voltage regime, such non-homogenous surface potential leads to the co-existence of electron and hole in an undoped semiconductor, while at higher voltages, the carrier concentration in the semiconductor becomes electron dominated. In addition, we show that with FE being in the 180 MD state, the minimum potential at FE-DE interface and hence, the minimum surface potential in the semiconductor, does not exceed the applied voltage (in-spite of the local differential amplification and charge enhancement).