System Performance with varying L1 Instruction and Data Cache Sizes: An Empirical Analysis

TL;DR

This paper empirically analyzes how varying L1 instruction and data cache sizes affect system performance using simulation with the Gem5 framework and the PARSEC benchmark.

Contribution

It provides an empirical evaluation of the impact of L1 cache size variations on system performance metrics in a simulated environment.

Findings

Performance varies with cache size changes

Optimal cache sizes improve hit rates and reduce latency

Discrepancies between expectations and observed results are discussed

Abstract

In this project, we investigate the fluctuations in performance caused by changing the Instruction (I-cache) size and the Data (D-cache) size in the L1 cache. We employ the Gem5 framework to simulate a system with varying specifications on a single host machine. We utilize the FreqMine benchmark available under the PARSEC suite as the workload program to benchmark our simulated system. The Out-order CPU (O3) with Ruby memory model was simulated in a Full-System X86 environment with Linux OS. The chosen metrics deal with Hit Rate, Misses, Memory Latency, Instruction Rate, and Bus Traffic within the system. Performance observed by varying L1 size within a certain range of values was used to compute Confidence Interval based statistics for relevant metrics. Our expectations, corresponding experimental observations, and discrepancies are also discussed in this report.