Efficient Hardware Implementation of Incremental Learning and Inference on Chip

TL;DR

This paper presents an FPGA-based hardware implementation of an incremental learning method that enables on-chip learning and inference with high efficiency, low resource use, and significant speedup over CPU processing.

Contribution

It introduces a novel hardware design for incremental learning combining transfer learning, majority voting, and quantization, capable of updating on new examples and classes directly on-chip.

Findings

Achieves state-of-the-art performance in incremental learning tasks.

Requires limited FPGA resources for implementation.

Provides significant acceleration over CPU-based processing.

Abstract

In this paper, we tackle the problem of incrementally learning a classifier, one example at a time, directly on chip. To this end, we propose an efficient hardware implementation of a recently introduced incremental learning procedure that achieves state-of-the-art performance by combining transfer learning with majority votes and quantization techniques. The proposed design is able to accommodate for both new examples and new classes directly on the chip. We detail the hardware implementation of the method (implemented on FPGA target) and show it requires limited resources while providing a significant acceleration compared to using a CPU.