All-Spin Bayesian Neural Networks

TL;DR

This paper introduces an all-spin hardware accelerator for Bayesian neural networks, leveraging spintronic devices to improve energy efficiency in probabilistic machine learning tasks.

Contribution

It presents the first hardware implementation of Bayesian neural networks using spintronic technology, demonstrating significant energy savings.

Findings

24x reduction in energy consumption compared to CMOS baseline

Development of a co-simulation framework for device-circuit-algorithm integration

First exploration of Bayesian neural hardware with emerging post-CMOS technologies

Abstract

Probabilistic machine learning enabled by the Bayesian formulation has recently gained significant attention in the domain of automated reasoning and decision-making. While impressive strides have been made recently to scale up the performance of deep Bayesian neural networks, they have been primarily standalone software efforts without any regard to the underlying hardware implementation. In this paper, we propose an "All-Spin" Bayesian Neural Network where the underlying spintronic hardware provides a better match to the Bayesian computing models. To the best of our knowledge, this is the first exploration of a Bayesian neural hardware accelerator enabled by emerging post-CMOS technologies. We develop an experimentally calibrated device-circuit-algorithm co-simulation framework and demonstrate $24\times$ reduction in energy consumption against an iso-network CMOS baseline implementation.