Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints
Mehrzad Nejat, Madhavan Manivannan, Miquel Pericas, Per Stenstrom

TL;DR
This paper introduces a coordinated resource management framework that optimizes energy efficiency in multicore systems by jointly managing cache partitioning, processor adaptation, and voltage-frequency scaling, leveraging instruction and memory-level parallelism.
Contribution
It presents a systematic study of resource trade-offs and a new management framework that significantly improves energy savings while maintaining QoS constraints.
Findings
Up to 18% energy savings achieved.
Average 10% energy savings across tested scenarios.
Effective modeling of MLP impact on performance.
Abstract
An effective way to improve energy efficiency is to throttle hardware resources to meet a certain performance target, specified as a QoS constraint, associated with all applications running on a multicore system. Prior art has proposed resource management (RM) frameworks in which the share of the last-level cache (LLC) assigned to each processor and the voltage-frequency (VF) setting for each processor is managed in a coordinated fashion to reduce energy. A drawback of such a scheme is that, while one core gives up LLC resources for another core, the performance drop must be compensated by a higher VF setting which leads to a quadratic increase in energy consumption. By allowing each core to be adapted to exploit instruction and memory-level parallelism (ILP/MLP), substantially higher energy savings are enabled. This paper proposes a coordinated RM for LLC partitioning, processor…
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