Machine Learning for high speed channel optimization

TL;DR

This paper introduces a Bayesian optimization approach to efficiently and accurately optimize PCB stack-up parameters, reducing costs and improving high-speed circuit performance.

Contribution

It presents a novel global optimization method combining parallel and intelligent Bayesian techniques specifically for stripline PCB design.

Findings

Improved optimization efficiency over traditional methods

Reduced PCB material costs in high-speed designs

Enhanced accuracy in impedance and crosstalk control

Abstract

Design of printed circuit board (PCB) stack-up requires the consideration of characteristic impedance, insertion loss and crosstalk. As there are many parameters in a PCB stack-up design, the optimization of these parameters needs to be efficient and accurate. A less optimal stack-up would lead to expensive PCB material choices in high speed designs. In this paper, an efficient global optimization method using parallel and intelligent Bayesian optimization is proposed for the stripline design.