Threshold Voltage variation with respect to Gate geometry in Nano-scale MOSFETS

TL;DR

This paper investigates how variations in Fin architecture and gate length in nano-scale MOSFETs affect threshold voltage, addressing variability and leakage issues in advanced semiconductor devices.

Contribution

It provides a detailed analysis of the impact of gate geometry changes on threshold voltage in nano-scale MOSFETs, highlighting effects on device variability.

Findings

Threshold voltage varies significantly with Fin architecture.

Gate length reduction influences threshold voltage stability.

Variability impacts device yield and performance.

Abstract

The tremendous progress in Metal Oxide Semiconductor (MOS) technology has been a direct consequence of device scaling for past several decades. But as we have entered the nanometer era many problems related to leakage currents and other issues related to variability impacting the yield are of concern. Herein we have investigated how the change in the Fin Architecture and Gate Length of the MOS device impacts the Threshold Voltage.