On Neural Architecture Search for Resource-Constrained Hardware Platforms
Qing Lu, Weiwen Jiang, Xiaowei Xu, Yiyu Shi, Jingtong Hu

TL;DR
This paper introduces a joint search framework for neural architecture, hardware implementation, and quantization to optimize neural networks for resource-constrained FPGA platforms, significantly improving accuracy and efficiency.
Contribution
It proposes a novel integrated approach to simultaneously optimize neural architecture, hardware implementation, and quantization, surpassing traditional sequential design methods.
Findings
Achieved 18-68% higher accuracy on CIFAR10 compared to traditional methods.
Found lightweight designs with 82.98% accuracy at high throughput using limited FPGA resources.
Demonstrated the framework's effectiveness under strict hardware constraints.
Abstract
In the recent past, the success of Neural Architecture Search (NAS) has enabled researchers to broadly explore the design space using learning-based methods. Apart from finding better neural network architectures, the idea of automation has also inspired to improve their implementations on hardware. While some practices of hardware machine-learning automation have achieved remarkable performance, the traditional design concept is still followed: a network architecture is first structured with excellent test accuracy, and then compressed and optimized to fit into a target platform. Such a design flow will easily lead to inferior local-optimal solutions. To address this problem, we propose a new framework to jointly explore the space of neural architecture, hardware implementation, and quantization. Our objective is to find a quantized architecture with the highest accuracy that is…
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Taxonomy
TopicsNeural Networks and Applications · Advanced Control Systems Optimization · Fault Detection and Control Systems
MethodsTest · Sigmoid Activation · Tanh Activation · Softmax · Long Short-Term Memory
