A firmware oriented trigger algorithm for CMS Drift Tubes in HL-LHC

TL;DR

This paper presents a new FPGA-compatible trigger algorithm for CMS Drift Tubes, enhancing muon detection precision and system performance in the high-luminosity environment of the HL-LHC.

Contribution

The paper introduces a novel FPGA-friendly trigger algorithm that improves muon segment reconstruction accuracy using full chamber information in the CMS Drift Tube system.

Findings

Algorithm achieves maximum resolution of DT chambers

Simulation results demonstrate improved muon reconstruction

Prototype implementation confirms feasibility and performance

Abstract

A full replacement of the existing muon trigger system in the CMS (Compact Muon Solenoid) detector is planned for operating at the maximum instantaneous luminosities of about $5-7.5\times10^{34}$ cm$^{-2}$ s$^{-1}$ expected in HL-LHC (High Luminosity Large Hadron Collider). In this plan, the new on-detector electronics that is being designed for the DT (Drift Tubes) detector will read out all the chamber information at its maximum time resolution. A new trigger system, based on the highest performing FPGAs, is being designed and will be capable of providing precise muon reconstruction and bunch crossing identification. An algorithm easily portable to an FPGA architecture has been designed to implement the new trigger primitive information from the DT detector. This algorithm reconstructs muon segments from single-wire DT hits, which contain a time uncertainty of 400 ns due to the drift time in the cell. This algorithm provides the maximum resolution achievable by the DT chambers and brings the hardware system closer to the offline performance capabilities. The results of the simulation and of the first implementations in the new electronics test bench will be shown.