Scalable High Performance SDN Switch Architecture on FPGA for Core Networks

TL;DR

This paper introduces a fully hardware-implemented FPGA-based SDN switch architecture compliant with OpenFlow, capable of processing 10Gbps packets and scaling up to 400Gbps with efficient resource utilization for core networks.

Contribution

It presents a novel FPGA-based switch design that achieves high throughput and scalability while maintaining resource efficiency, advancing SDN hardware implementations.

Findings

OpenFlow packet processing at 10Gbps

Scales up to 400Gbps throughput

Uses only 60% FPGA resources

Abstract

Due to the increasing heterogeneity in network user requirements, dynamically varying day to day network traffic patterns and delay in-network service deployment, there is a huge demand for scalability and flexibility in modern networking infrastructure, which in return has paved way for the introduction of Software Defined Networking (SDN) in core networks. In this paper, we present an FPGA-based switch that is fully compliant with OpenFlow; the pioneering protocol for southbound interface of SDN. The switch architecture is completely implemented on hardware. The design consists of an OpenFlow Southbound agent which can process OpenFlow packets at a rate of 10Gbps. The proposed architecture speed scales up to 400Gbps while it consumes only 60% of resources on a Xilinx Virtex-7 featuring XC7VX485T FPGA.