Investigation of gating effect in Si spin MOSFET

TL;DR

This study explores how gate voltage influences spin accumulation in Si spin MOSFETs, revealing a significant voltage reduction at high bias due to phonon emission affecting mobility and spin lifetime.

Contribution

It demonstrates the impact of high electric bias on spin accumulation voltage and attributes the reduction to optical phonon emission, supported by a detailed model comparison.

Findings

Negative gate voltage reduces spin accumulation voltage at high bias.

High electric bias causes a drastic decrease in mobility and spin lifetime.

Optical phonon emission is responsible for the observed effects.

Abstract

A gate voltage application in a Si-based spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) modulates spin accumulation voltages, where both electrical conductivity and drift velocity are modified while keeping constant electric current. An unprecedented reduction in the spin accumulation voltages in a Si spin MOSFET under negative gate voltage applications is observed in a high electric bias current regime. To support our claim, the electric bias current dependence of the spin accumulation voltage under the gate voltage applications is investigated in detail and compared to a spin drift diffusion model including the conductance mismatch effect. We proved that the drastic decrease of the mobility and spin lifetime in the Si channel is due to the optical phonon emission at the high electric bias current, which consequently reduced the spin accumulation voltage.