Comparing domain wall synapse with other Non Volatile Memory devices for on-chip learning in Analog Hardware Neural Network

TL;DR

This paper demonstrates that spin orbit torque driven Domain Wall (DW) devices outperform RRAM and PCM in on-chip learning for analog neural networks, offering more linear synaptic characteristics and significantly lower energy and time consumption.

Contribution

The study introduces the use of DW devices as synapses in neural networks, showing their advantages over RRAM and PCM in terms of linearity, symmetry, and efficiency for on-chip learning.

Findings

DW synapse has more linear and symmetric characteristics.

DW-based neural networks require significantly less energy and time for training.

Successful on-chip learning demonstrated on Fisher's Iris dataset.

Abstract

Resistive Random Access Memory (RRAM) and Phase Change Memory (PCM) devices have been popularly used as synapses in crossbar array based analog Neural Network (NN) circuit to achieve more energy and time efficient data classification compared to conventional computers. Here we demonstrate the advantages of recently proposed spin orbit torque driven Domain Wall (DW) device as synapse compared to the RRAM and PCM devices with respect to on-chip learning (training in hardware) in such NN. Synaptic characteristic of DW synapse, obtained by us from micromagnetic modeling, turns out to be much more linear and symmetric (between positive and negative update) than that of RRAM and PCM synapse. This makes design of peripheral analog circuits for on-chip learning much easier in DW synapse based NN compared to that for RRAM and PCM synapses. We next incorporate the DW synapse as a Verilog-A model in the crossbar array based NN circuit we design on SPICE circuit simulator. Successful on-chip learning is demonstrated through SPICE simulations on the popular Fisher's Iris dataset. Time and energy required for learning turn out to be orders of magnitude lower for DW synapse based NN circuit compared to that for RRAM and PCM synapse based NN circuits.