LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference
Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A., Constantinides

TL;DR
LUTNet leverages FPGA LUTs as flexible inference operators, enabling highly area- and energy-efficient neural network deployment with significant pruning and comparable accuracy to binarized networks.
Contribution
This work introduces LUTNet, a novel FPGA framework that uses native LUTs for neural network inference, allowing for greater pruning and efficiency improvements.
Findings
Up to twice the area efficiency compared to state-of-the-art binarized networks.
Significant area savings with comparable accuracy.
Enhanced energy efficiency in FPGA-based neural network inference.
Abstract
Research has shown that deep neural networks contain significant redundancy, and thus that high classification accuracy can be achieved even when weights and activations are quantized down to binary values. Network binarization on FPGAs greatly increases area efficiency by replacing resource-hungry multipliers with lightweight XNOR gates. However, an FPGA's fundamental building block, the K-LUT, is capable of implementing far more than an XNOR: it can perform any K-input Boolean operation. Inspired by this observation, we propose LUTNet, an end-to-end hardware-software framework for the construction of area-efficient FPGA-based neural network accelerators using the native LUTs as inference operators. We describe the realization of both unrolled and tiled LUTNet architectures, with the latter facilitating smaller, less power-hungry deployment over the former while sacrificing area and…
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Taxonomy
TopicsAdvanced Neural Network Applications · Advanced Memory and Neural Computing · Low-power high-performance VLSI design
MethodsPruning
