Automatic Generation of Multi-precision Multi-arithmetic CNN Accelerators for FPGAs

TL;DR

Tomato is an automated framework that generates efficient, multi-precision, multi-arithmetic CNN accelerators for FPGAs, enabling high throughput and low latency inference, including full ImageNet networks on a single FPGA.

Contribution

First auto-generation framework for multi-precision multi-arithmetic CNN accelerators on FPGAs, combining software fine-tuning with hardware design for optimized performance.

Findings

Achieves 2-4x better latency and throughput than existing FPGA solutions.

Can pack a full ImageNet network onto a single FPGA without off-chip memory.

Runs ImageNet classification at over 3000 frames per second.

Abstract

Modern deep Convolutional Neural Networks (CNNs) are computationally demanding, yet real applications often require high throughput and low latency. To help tackle these problems, we propose Tomato, a framework designed to automate the process of generating efficient CNN accelerators. The generated design is pipelined and each convolution layer uses different arithmetics at various precisions. Using Tomato, we showcase state-of-the-art multi-precision multi-arithmetic networks, including MobileNet-V1, running on FPGAs. To our knowledge, this is the first multi-precision multi-arithmetic auto-generation framework for CNNs. In software, Tomato fine-tunes pretrained networks to use a mixture of short powers-of-2 and fixed-point weights with a minimal loss in classification accuracy. The fine-tuned parameters are combined with the templated hardware designs to automatically produce efficient inference circuits in FPGAs. We demonstrate how our approach significantly reduces model sizes and computation complexities, and permits us to pack a complete ImageNet network onto a single FPGA without accessing off-chip memories for the first time. Furthermore, we show how Tomato produces implementations of networks with various sizes running on single or multiple FPGAs. To the best of our knowledge, our automatically generated accelerators outperform closest FPGA-based competitors by at least 2-4x for lantency and throughput; the generated accelerator runs ImageNet classification at a rate of more than 3000 frames per second.