GraVF-M: Graph Processing System Generation for Multi-FPGA Platforms

TL;DR

GraVF-M is a framework that automatically generates optimized FPGA-based graph processing accelerators for multi-FPGA systems with distributed memory, significantly reducing inter-FPGA communication and achieving high throughput.

Contribution

It introduces an automated RTL code generation framework for multi-FPGA graph processing that reduces inter-FPGA traffic and simplifies implementation.

Findings

Achieves up to 5.8 GTEPS throughput on 4-FPGA system.

Reduces inter-FPGA network traffic by a factor of the graph's average degree.

Reaches 94% of the theoretical performance limit.

Abstract

Due to the irregular nature of connections in most graph datasets, partitioning graph analysis algorithms across multiple computational nodes that do not share a common memory inevitably leads to large amounts of interconnect traffic. Previous research has shown that FPGAs can outcompete software-based graph processing in shared memory contexts, but it remains an open question if this advantage can be maintained in distributed systems. In this work, we present GraVF-M, a framework designed to ease the implementation of FPGA-based graph processing accelerators for multi-FPGA platforms with distributed memory. Based on a lightweight description of the algorithm kernel, the framework automatically generates optimized RTL code for the whole multi-FPGA design. We exploit an aspect of the programming model to present a familiar message-passing paradigm to the user, while under the hood implementing a more efficient architecture that can reduce the necessary inter-FPGA network traffic by a factor equal to the average degree of the input graph. A performance model based on a theoretical analysis of the factors influencing performance serves to evaluate the efficiency of our implementation. With a throughput of up to 5.8 GTEPS (billions of traversed edges per second) on a 4-FPGA system, the designs generated by GraVF-M compare favorably to state-of-the-art frameworks from the literature and reach 94% of the projected performance limit of the system.