Low Noise Cold Electronics System for SBND LAr TPC

TL;DR

This paper presents the development and testing of low-noise cold electronics for the SBND liquid argon TPC, enabling precise charge detection in a large-scale neutrino detector at cryogenic temperatures.

Contribution

It introduces a custom-designed cold front-end ASIC and integrated electronics system optimized for cryogenic operation in large LAr TPCs, with extensive testing and system integration.

Findings

Successful operation of cold electronics at 77 K to 300 K.

Low noise and high reliability achieved in the electronics system.

Effective integration of cold and warm electronics with diagnostics.

Abstract

The Short Baseline Near Detector (SBND) is one of three liquid argon (LAr) neutrino detectors sitting in the Booster Neutrino Beam (BNB) at Fermilab as part of the Short Baseline Neutrino (SBN) program. The detector is in a cryostat holding 260-ton of LAr and consists of four 2.5 m (L) $\times$ 4 m (W) Anode Plane Assembles (APAs) and two Cathode Plane Assemblies (CPAs), which leads to 11,264 Time Projection Chamber (TPC) readout channels and two separate 2 m long drift regions. As an enabling technology, Cold Electronics (CE) developed for cryogenic temperature operation makes possible an optimum balance among various design and performance requirements for such large sized detectors. Brookhaven National Laboratory (BNL) has been leading the R&D and implementation of the entire front-end CE system for LAr TPC readout in collaboration with other SBND institutes. The front-end readout electronics system includes the cold front-end electronics placed close to the wire electrodes, which detects and digitizes the charge signal in LAr, as well as the warm interface electronics placed on the signal feed-through flange outside of the cryostat, which further organizes and transmits the digitized signal to the DAQ system. An extensive study of electronics suitable for 77 K - 300 K, including the custom designed front-end ASIC and commercial components, e.g. ADC and FPGA, has been made to meet requirements such as low noise, low power consumption, high reliability and long lifetime. Furthermore, an integral design concept of APA, CE, feed-through, warm interface electronics with local diagnostics, grounding and isolation rules has been practiced with vertical slice test stands to make projection of the CE performance in the SBND detector.