Hardware/Software Codesign for Training/Testing Multiple Neural Networks on Multiple FPGAs

TL;DR

This paper introduces a flexible VHDL-based hardware/software co-design approach enabling the training and testing of multiple neural networks across multiple FPGAs, enhancing adaptability and scalability.

Contribution

The paper presents a novel VHDL structure that supports flexible implementation, training, and testing of multiple neural networks on multiple FPGAs, with a modular processor group design.

Findings

Supports multiple neural networks on multiple FPGAs

Enables training and testing within a unified VHDL framework

Uses processor groups with ring buffer connectivity

Abstract

Most neural network designs for FPGAs are inflexible. In this paper, we propose a flexible VHDL structure that would allow any neural network to be implemented on multiple FPGAs. Moreover, the VHDL structure allows for testing as well as training multiple neural networks. The VHDL design consists of multiple processor groups. There are two types of processor groups: Mini Vector Machine Processor Group and Activation Processor Group. Each processor group consists of individual Mini Vector Machines and Activation Processor. The Mini Vector Machines apply vector operations to the data, while the Activation Processors apply activation functions to the data. A ring buffer was implemented to connect the various processor groups.