Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA

TL;DR

This paper presents a flexible FPGA-based matrix multiplier that uses efficient algorithms and run-time reconfiguration to optimize power, delay, and precision for high-power computing tasks like image and signal processing.

Contribution

It introduces a novel run-time-reconfigurable floating-point multiplier with custom precision, combining multiple algorithms for efficient matrix multiplication on FPGA.

Findings

Achieves dynamic adjustment of power and delay based on precision needs

Employs efficient algorithms for matrix and binary multiplication

Demonstrates suitability for high-power computing applications

Abstract

In todays world, high-power computing applications such as image processing, digital signal processing, graphics, and robotics require enormous computing power. These applications use matrix operations, especially matrix multiplication. Multiplication operations require a lot of computational time and are also complex in design. We can use field-programmable gate arrays as low-cost hardware accelerators along with a low-cost general-purpose processor instead of a high-cost application-specific processor for such applications. In this work, we employ an efficient Strassens algorithm for matrix multiplication and a highly efficient run-time-reconfigurable floating-point multiplier for matrix element multiplication. The run-time-reconfigurable floating-point multiplier is implemented with custom floating-point format for variable-precision applications. A very efficient combination of Karatsuba algorithm and Urdhva Tiryagbhyam algorithm is used to implement the binary multiplier. This design can effectively adjust the power and delay requirements according to different accuracy requirements by reconfiguring itself during run time.