A Novel Low Power Non-Volatile SRAM Cell with Self Write Termination

TL;DR

This paper introduces a low power non-volatile SRAM cell utilizing STT-MTJ devices with a novel self write termination circuit, significantly reducing power consumption and transistor count for standby applications.

Contribution

It presents a new non-volatile SRAM design with an integrated write termination circuit that enhances power efficiency and reduces transistor count.

Findings

25.81% reduction in transistor count

2.95% decrease in power consumption

Effective non-volatile storage during standby

Abstract

A non-volatile SRAM cell is proposed for low power applications using Spin Transfer Torque-Magnetic Tunnel Junction (STT-MTJ) devices. This novel cell offers non-volatile storage, thus allowing selected blocks of SRAM to be switched off during standby operation. To further increase the power savings, a write termination circuit is designed which detects completion of MTJ write and closes the bidirectional current path for the MTJ. A reduction of 25.81% in the number of transistors and a reduction of 2.95% in the power consumption is achieved in comparison to prior work on write termination circuits.