Improvement in Retention Time of Capacitorless DRAM with Access Transistor

TL;DR

This paper introduces a novel capacitorless DRAM cell using junctionless transistors and an access transistor, significantly improving retention time and sense margin, especially at scaled gate lengths.

Contribution

It proposes a junctionless/accumulation mode transistor-based capacitorless DRAM cell with enhanced retention time and scalability over conventional designs.

Findings

Achieved a maximum sense margin of ~4.6 μA/μm and retention time of ~6.5 seconds at 100 nm gate length.

Demonstrated scalability with retention times of ~100 ms and ~10 ms at 10 nm gate length at different temperatures.

Showed improved gate length scalability and reduced leakage in the proposed DRAM cell.

Abstract

In this paper, we propose a Junctionless (JL)/Accumulation Mode (AM) transistor with an access transistor (JL in series with JL/AM transistor) based capacitorless Dynamic Random Access Memory (1TDRAM) cell. The JL transistor overcomes the problem of ultrasharp p-n junction associated with conventional Metal-Oxide-Semiconductor (MOS) in nanoscale regime. The access transistor (AT) is utilized to reduces the leakage, and thus, improves the Retention Time (RT) and Sense Margin (SM) of the proposed capacitorless DRAM cell. Thus, the proposed DRAM cell achieved a maximum SM of ~4.6 {\mu}A/{\mu}m with RT of ~6.5 s for a gate length (Lg) of 100nm. Further, this topology shows better gate length scalability with a fixed gate length of AT and achieves RT of ~100 ms and ~10 ms for a scaled gate length of 10 nm at 27 {\deg}C and 85 {\deg}C, respectively.