An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm

TL;DR

This paper introduces a high-speed, power-efficient floating point multiplier for IEEE 754 standard, combining Karatsuba and Urdhva-Tiryagbhyam algorithms to optimize FPGA implementation.

Contribution

It presents a novel combination of algorithms for floating point multiplication that improves delay and power consumption in FPGA designs.

Findings

Reduced delay in floating point multiplication

Lower power consumption compared to traditional methods

Successful FPGA implementation on Spartan-3E and Virtex-4

Abstract

Floating point multiplication is a crucial operation in high power computing applications such as image processing, signal processing etc. And also multiplication is the most time and power consuming operation. This paper proposes an efficient method for IEEE 754 floating point multiplication which gives a better implementation in terms of delay and power. A combination of Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm (Vedic Mathematics) is used to implement unsigned binary multiplier for mantissa multiplication. The multiplier is implemented using Verilog HDL, targeted on Spartan-3E and Virtex-4 FPGA.