CMOS Platform for Atomic-Scale Device Fabrication

TL;DR

This paper presents a CMOS-compatible platform for atomic-scale device fabrication that simplifies the process, reduces fabrication time, and enables integration of STM-patterned dopant devices into complex architectures, demonstrated through Si:P nanowires.

Contribution

It introduces a novel CMOS-compatible process flow for atomic-scale device fabrication using STM patterning on silicon on insulator substrates.

Findings

Successful fabrication of degenerately doped Si:P nanowires.

Room temperature magnetotransport measurements confirm device functionality.

Reduced process complexity and fabrication time.

Abstract

Controlled atomic scale fabrication of functional devices is one of the holy grails of nanotechnology. The most promising class of techniques that enable deterministic nanodevice fabrication are based on scanning probe patterning or surface assembly. However, this typically involves a complex process flow, stringent requirements for an ultra high vacuum environment, long fabrication times and, consequently, limited throughput and device yield. Here, a device platform is developed that overcomes these limitations by integrating scanning probe based dopant device fabrication with a CMOS-compatible process flow. Silicon on insulator substrates are used featuring a reconstructed Si(001):H surface that is protected by a capping chip and has pre-implanted contacts ready for scanning tunneling microscope (STM) patterning. Processing in ultra-high vacuum is thus reduced to only a few critical steps which minimizes the complexity, time and effort required for fabrication of the nanoscale dopant devices. Subsequent reintegration of the samples into the CMOS process flow not only simplifies the post-processing but also opens the door to successful application of STM based dopant devices as a building block in more complex device architectures. Full functionality of this approach is demonstrated with magnetotransport measurements on degenerately doped STM patterned Si:P nanowires up to room temperature.