ARCHITECT: Arbitrary-precision Hardware with Digit Elision for Efficient Iterative Compute
He Li, James J. Davis, John Wickerson, George A., Constantinides

TL;DR
ARCHITECT introduces a novel hardware approach using most-significant digit-first arithmetic to efficiently perform arbitrary-precision iterative computations, enabling dynamic digit stability detection and significant performance and memory improvements.
Contribution
The paper presents a new hardware design that leverages most-significant digit-first arithmetic for iterative algorithms, allowing arbitrary precision and runtime digit stability detection.
Findings
Up to 16× performance speedup compared to traditional arbitrary-precision solvers.
Approximately 1.9× reduction in memory usage.
Demonstrated efficiency gains in evaluated benchmarks.
Abstract
Many algorithms feature an iterative loop that converges to the result of interest. The numerical operations in such algorithms are generally implemented using finite-precision arithmetic, either fixed- or floating-point, most of which operate least-significant digit first. This results in a fundamental problem: if, after some time, the result has not converged, is this because we have not run the algorithm for enough iterations or because the arithmetic in some iterations was insufficiently precise? There is no easy way to answer this question, so users will often over-budget precision in the hope that the answer will always be to run for a few more iterations. We propose a fundamentally new approach: with the appropriate arithmetic able to generate results from most-significant digit first, we show that fixed compute-area hardware can be used to calculate an arbitrary number of…
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Taxonomy
TopicsNumerical Methods and Algorithms · Parallel Computing and Optimization Techniques · Digital Filter Design and Implementation
