Analysis and Design of a 32nm FinFET Dynamic Latch Comparator

TL;DR

This paper analyzes and designs a 32nm FinFET dynamic latch comparator, proposing a new structure that improves power efficiency, delay, and offset voltage compared to recent designs, using LTspice simulations.

Contribution

It introduces a novel dynamic latch comparator structure implemented in 32nm FinFET technology, enhancing performance metrics over existing designs.

Findings

Reduced power consumption

Lower delay time

Improved power delay product

Abstract

Comparators have multifarious applications in various fields, especially used in analog to digital converters. Over the years, we have seen many different designs of single stage, dynamic latch type and double tail type comparators based on CMOS technology, and all of them had to make the tradeoff between power consumption and delay time. Meanwhile, to mitigate the short channel effects of conventional CMOS based design, FinFET has emerged as the most promising alternative by owning the tremendous gate control feature over the channel region. In this paper, we have analyzed the performance of some recent dynamic latch type comparators and proposed a new structure of dynamic latch comparator; moreover, 32nm FinFET technology has been considered as the common platform for all of the comparators circuit design. The proposed comparator has shown impressive performance in case of power consumption, time delay, power delay product and offset voltage while compared with the other recent comparators through simulations with LTspice.