System-level optimization of Network-on-Chips for heterogeneous 3D System-on-Chips

TL;DR

This paper presents a heuristic for system-level optimization of 3D heterogeneous Network-on-Chips, integrating application and technology parameters, resulting in significant reductions in white space and improved network performance.

Contribution

It introduces a novel integrated optimization problem and a heuristic solution based on separating intra- and interlayer communication for 3D SoC design.

Findings

Up to 18.8% reduction in white space.

Up to 12.4% improvement in network performance.

Validated with 3D Vision SoC case studies.

Abstract

For a system-level design of Networks-on-Chip for 3D heterogeneous System-on-Chip (SoC), the locations of components, routers and vertical links are determined from an application model and technology parameters. In conventional methods, the two inputs are accounted for separately; here, we define an integrated problem that considers both application model and technology parameters. We show that this problem does not allow for exact solution in reasonable time, as common for many design problems. Therefore, we contribute a heuristic by proposing design steps, which are based on separation of intralayer and interlayer communication. The advantage is that this new problem can be solved with well-known methods. We use 3D Vision SoC case studies to quantify the advantages and the practical usability of the proposed optimization approach. We achieve up to 18.8% reduced white space and up to 12.4% better network performance in comparison to conventional approaches.