Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications

TL;DR

This paper introduces a run-time reconfigurable FPGA-based floating point multiplier with custom formats and multiple modes, optimized for high speed and low power across diverse applications.

Contribution

It presents a novel FPGA implementation of a multi-mode, run-time reconfigurable floating point multiplier using custom formats and efficient algorithms.

Findings

Supports 6 operational modes for different accuracy and power needs.

Uses custom IPs and input truncation for optimized performance.

Employs Karatsuba and Vedic algorithms for efficient multiplication.

Abstract

Floating point multiplication is one of the crucial operations in many application domains such as image processing, signal processing etc. But every application requires different working features. Some need high precision, some need low power consumption, low latency etc. But IEEE-754 format is not really flexible for these specifications and also design is complex. Optimal run-time reconfigurable hardware implementations may need the use of custom floating-point formats that do not necessarily follow IEEE specified sizes. In this paper, we present a run-time-reconfigurable floating point multiplier implemented on FPGA with custom floating point format for different applications. This floating point multiplier can have 6 modes of operations depending on the accuracy or application requirement. With the use of optimal design with custom IPs (Intellectual Properties), a better implementation is done by truncating the inputs before multiplication. And a combination of Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm (Vedic Mathematics) is used to implement unsigned binary multiplier. This further increases the efficiency of the multiplier.