Understanding Quantum Control Processor Capabilities and Limitations through Circuit Characterization

TL;DR

This paper introduces a methodology to evaluate quantum control processor instruction set architectures (ISAs) for intermediate-scale quantum devices, focusing on performance, scalability, and real-time operation capabilities.

Contribution

It presents a quantitative assessment framework for quantum ISAs and proposes new scalar and vector ISA extensions, comparing their efficiency and scalability.

Findings

QUASAR and qV outperform existing ISAs in encoding efficiency

Proposed ISAs meet real-time gate cycle requirements

Framework guides future quantum control hardware design

Abstract

Continuing the scaling of quantum computers hinges on building classical control hardware pipelines that are scalable, extensible, and provide real time response. The instruction set architecture (ISA) of the control processor provides functional abstractions that map high-level semantics of quantum programming languages to low-level pulse generation by hardware. In this paper, we provide a methodology to quantitatively assess the effectiveness of the ISA to encode quantum circuits for intermediate-scale quantum devices with O($10^2$) qubits. The characterization model that we define reflects performance, the ability to meet timing constraint implications, scalability for future quantum chips, and other important considerations making them useful guides for future designs. Using our methodology, we propose scalar (QUASAR) and vector (qV) quantum ISAs as extensions and compare them with other ISAs in metrics such as circuit encoding efficiency, the ability to meet real-time gate cycle requirements of quantum chips, and the ability to scale to more qubits.