Readout Electronics of T0 Detector in the External Target Experiment of CSR in HIRFL

TL;DR

This paper presents the design and testing of a high-precision readout electronics system for the T0 detector in the CSR external target experiment, achieving better than 21 ps timing resolution.

Contribution

The paper introduces a novel readout electronics system based on NINO ASIC and FPGA for the T0 detector, demonstrating high precision and reliable performance.

Findings

Electronics system achieves better than 21 ps timing resolution.

System functions well in tests, meeting application requirements.

Effective charge-to-time conversion and discrimination implemented.

Abstract

T0 detector, based on Multi-gap Resistive Plate Chambers (MRPC) technology, is one of the key components in the External Target Experiment. Through precision measurements of the MRPC signals, timing of the beam impact on target can be obtained and used as the start time for other detectors. A readout electronics system was designed for the T0 detector. Based on the NINO ASIC, front-end-electronics (FEE) circuits which can achieve high precision leading-edge discrimination and Charge-to-Time Conversion (QTC) were designed for the internal and external MRPCs of the T0 detector. The output pulse of the FEE is then digitized by high precision time digitization modules with Time-to-Digital Converters (TDCs), trigger matching and other control logic integrated within Field Programmable Gate Array (FPGA) devices. To evaluate the functionality and performance, we also conducted a series of tests of the electronics. Results indicate that the system functions well and the time precision of the electronics is better than 21 ps, which satisfies the application requirement.