Improving wafer-scale Josephson junction resistance variation in superconducting quantum coherent circuits

TL;DR

This paper presents an optimized fabrication process that significantly reduces variation in Josephson junction resistance across wafer-scale superconducting circuits, enhancing qubit uniformity and device yield.

Contribution

The authors develop a systematic process improvement that reduces critical current variation to below 3.5% across large wafer areas, enabling more reliable superconducting quantum circuits.

Findings

Achieved less than 3.5% RSD in critical current across 49 cm²

Within 1x1 cm areas, variation as low as 1.8% RSD

Process improvements lead to higher yield of multi-junction qubit chips

Abstract

Quantum bits, or qubits, are an example of coherent circuits envisioned for next-generation computers and detectors. A robust superconducting qubit with a coherent lifetime of $O$(100 $\mu$s) is the transmon: a Josephson junction functioning as a non-linear inductor shunted with a capacitor to form an anharmonic oscillator. In a complex device with many such transmons, precise control over each qubit frequency is often required, and thus variations of the junction area and tunnel barrier thickness must be sufficiently minimized to achieve optimal performance while avoiding spectral overlap between neighboring circuits. Simply transplanting our recipe optimized for single, stand-alone devices to wafer-scale (producing 64, 1x1 cm dies from a 150 mm wafer) initially resulted in global drifts in room-temperature tunneling resistance of $\pm$ 30%. Inferring a critical current $I_{\rm c}$ variation from this resistance distribution, we present an optimized process developed from a systematic 38 wafer study that results in $<$ 3.5% relative standard deviation (RSD) in critical current ($\equiv \sigma_{I_{\rm c}}/\left\langle I_{\rm c} \right\rangle$) for 3000 Josephson junctions (both single-junctions and asymmetric SQUIDs) across an area of 49 cm$^2$. Looking within a 1x1 cm moving window across the substrate gives an estimate of the variation characteristic of a given qubit chip. Our best process, utilizing ultrasonically assisted development, uniform ashing, and dynamic oxidation has shown $\sigma_{I_{\rm c}}/\left\langle I_{\rm c} \right\rangle$ = 1.8% within 1x1 cm, on average, with a few 1x1 cm areas having $\sigma_{I_{\rm c}}/\left\langle I_{\rm c} \right\rangle$ $<$ 1.0% (equivalent to $\sigma_{f}/\left\langle f \right\rangle$ $<$ 0.5%). Such stability would drastically improve the yield of multi-junction chips with strict critical current requirements.