Fault-tolerant Quantum Error Correction on Near-term Quantum Processors using Flag and Bridge Qubits

TL;DR

This paper introduces a flag-bridge quantum error correction method tailored for near-term quantum processors with limited qubits and connectivity, demonstrating improved fault tolerance and lower logical error rates.

Contribution

It combines flag fault tolerance with circuit mapping to create an efficient error correction scheme suitable for small, noisy quantum devices.

Findings

Flag-bridge approach reduces logical error rates.

Steane code can outperform surface code with this method.

Simulation confirms effectiveness on current superconducting processors.

Abstract

Fault-tolerant (FT) computation by using quantum error correction (QEC) is essential for realizing large-scale quantum algorithms. Devices are expected to have enough qubits to demonstrate aspects of fault tolerance in the near future. However, these near-term quantum processors will only contain a small amount of noisy qubits and allow limited qubit connectivity. Fault-tolerant schemes that not only have low qubit overhead but also comply with geometrical interaction constraints are therefore necessary. In this work, we combine flag fault tolerance with quantum circuit mapping, to enable an efficient flag-bridge approach to implement FT QEC on near-term devices. We further show an example of performing the Steane code error correction on two current superconducting processors and numerically analyze their performance with circuit level noise. The simulation results show that the QEC circuits that measure more stabilisers in parallel have lower logical error rates. We also observe that the Steane code can outperform the distance-3 surface code using flag-bridge error correction. In addition, we foresee potential applications of the flag-bridge approach such as FT computation using lattice surgery and code deformation techniques.