Instructional Level Parallelism
Taposh Dutta-Roy
TL;DR
This paper reviews the evolution of instruction level parallelism, discussing challenges like pipelining dependencies and exploring future research directions to enhance execution speed.
Contribution
It provides a comprehensive overview of instruction level parallelism developments, including solutions to pipelining issues and insights into future research trends.
Findings
Analysis of pipelining drawbacks and solutions
Overview of recent advancements in instruction parallelism
Discussion of future research directions
Abstract
This paper is a review of the developments in Instruction level parallelism. It takes into account all the changes made in speeding up the execution. The various drawbacks and dependencies due to pipelining are discussed and various solutions to overcome them are also incorporated. It goes ahead in the last section to explain where is the new research leading us.
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Taxonomy
TopicsParallel Computing and Optimization Techniques · Network Packet Processing and Optimization · Low-power high-performance VLSI design