An SR Flip-Flop based Physical Unclonable Functions for Hardware Security

TL;DR

This paper introduces a novel SR flip-flop based PUF design leveraging process variations for secure IC identification, suitable for IoT devices with minimal area and power overhead.

Contribution

A new NAND-based SR flip-flop PUF design that utilizes race conditions and process variations for robust hardware security identification.

Findings

Robust PUF responses across 90nm, 45nm, and 32nm nodes.

Low overhead in power, timing, and area.

Effective in diverse design scenarios and corners.

Abstract

Physical Unclonable Functions (PUFs) have emerged as a promising solution to identify and authenticate Integrated Circuits (ICs). In this paper, we propose a novel NAND-based Set-Reset (SR) Flip-flop (FF) PUF design for security enclosures of the area- and power-constrained Internet-of-Things (IoT) edge node. Such SR-FF based PUF is constructed during a unique race condition that is (normally) avoided due to inconsistency. We have shown, when both inputs (S and R) are logic high ('1') and followed by logic zero ('0'), the outputs Q and Qbar can settle down to either 0 or 1 or vice-versa depending on statistical delay variations in cross-coupled paths. We incorporate the process variations during SPICE-level simulations to leverage the capability of SR-FF in generating the unique identifier of an IC. Experimental results for 90nm, 45nm, and 32nm process nodes show the robustness of SR-FF PUF responses in terms of uniqueness, randomness, uniformity, and bit(s) biases. Furthermore, we perform physical synthesis to evaluate the applicability of SR FF PUF on five designs from OpenCores in three design corners. The estimated overhead for power, timing, and area in three design corners are negligible.