A Novel Design of Adaptive and Hierarchical Convolutional Neural Networks using Partial Reconfiguration on FPGA
Mohammad Farhadi, Mehdi Ghasemi, Yezhou Yang

TL;DR
This paper presents an adaptive CNN architecture on FPGA that switches between shallow and deep networks using partial reconfiguration to optimize throughput and resource use on embedded devices.
Contribution
It introduces a novel adaptive CNN design with a gating mechanism and partial reconfiguration to efficiently balance accuracy and resource constraints on FPGA-based systems.
Findings
Achieves around 400 images/sec throughput on SVHN dataset.
Reduces deep network computation to below 70% for CIFAR datasets.
Maintains accuracy while optimizing resource utilization.
Abstract
Nowadays most research in visual recognition using Convolutional Neural Networks (CNNs) follows the "deeper model with deeper confidence" belief to gain a higher recognition accuracy. At the same time, deeper model brings heavier computation. On the other hand, for a large chunk of recognition challenges, a system can classify images correctly using simple models or so-called shallow networks. Moreover, the implementation of CNNs faces with the size, weight, and energy constraints on the embedded devices. In this paper, we implement the adaptive switching between shallow and deep networks to reach the highest throughput on a resource-constrained MPSoC with CPU and FPGA. To this end, we develop and present a novel architecture for the CNNs where a gate makes the decision whether using the deeper model is beneficial or not. Due to resource limitation on FPGA, the idea of partial…
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