NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures

TL;DR

This paper addresses the challenges of communication in heterogeneous 3D SoCs by co-designing routing algorithms and microarchitectures, significantly improving throughput and latency while reducing power consumption.

Contribution

It introduces technology-aware models for heterogeneous layers, proposes two novel routing algorithms, and designs a microarchitecture that overcomes heterogeneity limitations.

Findings

Routing algorithms improve latency by up to 6.5x.

Throughput increases by 2 to 4x with the new microarchitecture.

Router power consumption decreases by up to 41.1%.

Abstract

Heterogeneous 3D System-on-Chips (3D SoCs) are the most promising design paradigm to combine sensing and computing within a single chip. A special characteristic of communication networks in heterogeneous 3D SoCs is the varying latency and throughput in each layer. As shown in this work, this variance drastically degrades the network performance. We contribute a co-design of routing algorithms and router microarchitecture that allows to overcome these performance limitations. We analyze the challenges of heterogeneity: Technology-aware models are proposed for communication and thereby identify layers in which packets are transmitted slower. The communication models are precise for latency and throughput under zero load. The technology model has an area error and a timing error of less than 7.4% for various commercial technologies from 90 to 28nm. Second, we demonstrate how to overcome limitations of heterogeneity by proposing two novel routing algorithms called Z+(XY)Z- and ZXYZ that enhance latency by up to 6.5x compared to conventional dimension order routing. Furthermore, we propose a high vertical-throughput router microarchitecture that is adjusted to the routing algorithms and that fully overcomes the limitations of slower layers. We achieve an increased throughput of 2 to 4x compared to a conventional router. Thereby, the dynamic power of routers is reduced by up to 41.1% and we achieve improved flit latency of up to 2.26x at small total router area costs between 2.1% and 10.4% for realistic technologies and application scenarios.