FLAG: A Framework for FPGA-based LoAd Generation in Profinet Communication

TL;DR

This paper presents FLAG, an FPGA-based framework for generating precise PROFINET traffic loads to test industrial Ethernet systems, ensuring robustness under high traffic conditions.

Contribution

The paper introduces a novel FPGA-based load generator for PROFINET, enabling accurate and configurable traffic simulation at line rates.

Findings

Capable of generating load at Fast/Gigabit line rate

Supports configuration of packet size, count, and Ethertypes

Accessible via web or command line interface

Abstract

Like other automated system technologies, PROFINET, a real-time Industrial Ethernet Standard has shown increasing level of integration into the present IT Infrastructure. Such vast use of PROFINET can expose the controllers and I/O devices to operate in critical failures when traffic goes unexpectedly higher than normal. Rigorous testing of the running devices then becomes essential and therefore, in this paper, we prototype and design an FPGA based load Generating solution called FLAG (FPGA-based LoAd Generator) for PROFINET based traffic at the desired load configurations such as, bits per second, the number and size of the packets with their Ethertypes and MAC addresses. We have employed, a Zynq-7000 FPGA as our implementation platform for the proposed FLAG framework. The system can easily be deployed and accessed via the web or command line interface for successful load generation. Extensive experiments have been conducted to verify the effectiveness of our proposed solution and the results confirm that the proposed framework is capable to generate precise load at Fast/Gigabit line rate with a defined number of packets.