Average-based Robustness for Continuous-Time Signal Temporal Logic

TL;DR

This paper introduces an average-based robustness score for continuous-time STL that considers the entire signal evolution, improving falsification and control synthesis in complex and multi-agent systems.

Contribution

It presents a novel robustness measure for STL that emphasizes the entire signal trajectory rather than just the most severe point, enhancing analysis accuracy.

Findings

Improved falsification success in complex systems.

Enhanced control synthesis performance.

Better robustness assessment over traditional methods.

Abstract

We propose a new robustness score for continuous-time Signal Temporal Logic (STL) specifications. Instead of considering only the most severe point along the evolution of the signal, we use average scores to extract more information from the signal, emphasizing robust satisfaction of all the specifications' subformulae over their entire time interval domains. We demonstrate the advantages of this new score in falsification and control synthesis problems in systems with complex dynamics and multi-agent systems.