Machine Learning Based Image Calibration for a Twofold Time-Interleaved High Speed DAC

TL;DR

This paper introduces a machine learning-inspired simulated annealing algorithm for calibrating a high-speed twofold time-interleaved DAC, effectively suppressing interleave images to noise floor in silicon implementation.

Contribution

It presents a novel image calibration algorithm based on simulated annealing for TIDAC, demonstrating practical effectiveness in silicon at 50 GS/s.

Findings

Successful suppression of interleave images to noise floor

Experimental validation on 14nm CMOS silicon chip

Achieved high-speed operation at 50 GS/s

Abstract

In this paper, we propose a novel image calibration algorithm for a twofold time-interleaved DAC (TIDAC). The algorithm is based on simulated annealing, which is often used in the field of machine learning to solve derivative free optimization (DFO) problems. The DAC under consideration is part of a digital transceiver core that contains a high speed ADC, microcontroller, and digital control via a serial peripheral interface (SPI). These are used as tools for designing an algorithm which suppresses the interleave image to the noise floor. The algorithm is supported with experimental results in silicon on a 10-bit twofold TIDAC operating at a sample rate of 50 GS/s in 14nm CMOS technology.