Domain Wall Enabled Steep Slope Switching in MoS$_2$ Transistors Towards Hysteresis-Free Operation

TL;DR

This paper demonstrates steep slope switching in MoS2 transistors enabled by domain wall dynamics in ferroelectric materials, achieving ultra-low voltage operation and subthreshold swing below the Boltzmann limit, advancing low-power 2D electronics.

Contribution

It reveals a hysteresis-free negative capacitance mechanism in MoS2 transistors driven by domain wall polar states, offering a new material strategy for low-power nanoelectronics.

Findings

Achieved subthreshold swing as low as 9.7 mV/decade at room temperature.

Demonstrated current on/off ratios up to 8×10^6 within ±0.5 V gate voltage.

Identified the role of domain wall polar states in enabling negative capacitance mode.

Abstract

The device concept of ferroelectric-based negative capacitance (NC) transistors offers a promising route for achieving energy-efficient logic applications that can outperform the conventional semiconductor technology, while viable operation mechanisms remain a central topic of debate. In this work, we report steep slope switching in MoS$_2$ transistors back-gated by single-layer polycrystalline PbZr$_{0.35}$Ti$_{0.65}$O$_3$. The devices exhibit current on/off ratios up to 8$\times$10$^6$ within an ultra-low gate voltage window of $V_g$ = $\pm$0.5 V and subthreshold swing (SS) as low as 9.7 mV decade$^{-1}$ at room temperature, transcending the 60 mV decade$^{-1}$ Boltzmann limit without involving additional dielectric layers. Theoretical modeling reveals the dominant role of the metastable polar states within domain walls in enabling the NC mode, which is corroborated by the relation between SS and domain wall density. Our findings shed light on a hysteresis-free mechanism for NC operation, providing a simple yet effective material strategy for developing low-power 2D nanoelectronics.