Porting of eChronos RTOS on RISC-V Architecture
Shubhendra Pal Singhal, M. Sridevi, N Sathya Narayanan, M J Shankar, Raman

TL;DR
This paper details the process and benefits of porting the formally verified eChronos RTOS to the open-source RISC-V architecture, enhancing security, reducing costs, and increasing transparency in embedded system development.
Contribution
The paper presents the first successful port of eChronos RTOS to RISC-V, including architectural modifications and open-source verification, expanding its applicability to open-source hardware.
Findings
eChronos was successfully ported to RISC-V and verified on spike.
Porting increases system security and reduces costs.
Open-source port is made available for community use.
Abstract
eChronos is a formally verified Real Time Operating System(RTOS) designed for embedded micro-controllers. eChronos was targeted for tightly constrained devices without memory management units. Currently, eChronos is available on proprietary designs like ARM, PowerPC and Intel architectures. eChronos is adopted in safety critical systems like aircraft control system and medical implant devices. eChronos is one of the very few system software not been ported to RISC-V. RISC-V is an open-source Instruction Set Architecture (ISA) that enables new era of processor development. Many standard Operating Systems, software tool chain have migrated to the RISC-V architecture. According to the latest trends, RISC-V is replacing many proprietary chips. As a secure RTOS, it is attractive to port on an open-source ISA. SHAKTI and PicoRV32 are some of the proven open-source RISC-V designs available.…
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Taxonomy
TopicsReal-Time Systems Scheduling · Embedded Systems Design Techniques · Radiation Effects in Electronics
