From design to tape-out in SCL 180nm CMOS integrated circuit fabrication technology

TL;DR

This paper provides a comprehensive guide for analog VLSI designers on preparing chip designs for fabrication at India's indigenous 180nm CMOS foundry, SCL Chandigarh, highlighting the design-to-tape-out process.

Contribution

It offers detailed procedural insights and practical guidance tailored for Indian researchers and designers to utilize the SCL 180nm CMOS fabrication facility effectively.

Findings

Successful design submission process detailed

Cost-effective fabrication options for Indian institutions

Enhanced understanding of tape-out procedures

Abstract

Although India has achieved considerable capability in electronic chip design, but developing the infrastructure for capital-intensive semiconductor fabrication remains a challenge. The rising domestic and global demand for electronics products, the need of enhancing the country's high-technology talent pool, employment generation, and national security concerns dictates the Indian Government's heightened efforts in promoting electronics hardware manufacturing in the country. A recent milestone in this regard is the setting up of 180nm CMOS fabrication facility at SCL, Chandigarh. The Multi Project Wafer runs of this indigenous foundry promises to be a relatively cost-effective option for Indian academic and R&D institutions in realizing their designed VLSI circuits. Written from the perspective of an Analog VLSI designer, this tutorial paper strives to provide all the requisite information and guidance that might be required in order to prepare chip designs for submission to SCL for fabrication.